Certain interconnect or bus architectures, such as Peripheral Component Interconnect Express (PCIe), implement a predetermined set of rules for ordering access requests, such as memory reads and writes, to a memory. When enforcing ordering rules, some access requests are suspended until receiving an indication that a previous access request is completed. Under certain applications, enforcement of ordering rules can prevent conflicts between different access requests, for example by preventing out-of-order access to a common address of the memory.